1. Field of the Invention
This invention relates to a voltage dropping circuit which is suitable for supplying electric power to an internal circuit formed by a submicron fabrication technique, and an integrated circuit using the voltage dropping circuit.
2. Prior Art
With the recent increase in density and operating speed of the integrated circuit, a so-called submicron fabrication technique has come to be more widely employed. According to the submicron fabrication technique, even more minuscule patterns are formed on a wafer than ones formed by conventional LSI fabrication techniques, so that the maximum permitted voltage of an oxide (SiO.sub.2) layer decreases. This limits the power supply voltage of an LSI fabricated by the submicron fabrication technique normally to a voltage of 3.3 volts. On the other hand, many LSI products employ a power supply voltage of 5 volts. To cope with this discrepancy, an LSI has been proposed, which is comprised of an I/O portion where an oxide layer with an increased thickness is used, and an internal circuit where an oxide layer with a reduced thickness employed by the submicron fabrication technique is used.
In the proposed LSI, the I/O portion operates on a power supply voltage of 5 volts, while the internal circuit on a power supply voltage of 3.3 volts, which means that two power supply systems are required. As a solution to this problem, the proposed LSI employs a voltage dropping circuit arranged therein, which drops a power supply voltage of 5 volts from an external power supply to a voltage suitable for the submicron internal circuit.
Now, the conventional voltage dropping circuit will be described with reference to FIG. 1. As shown in the figure, an operational amplifier 1 has an output terminal thereof connected to the gate of an FET (field effect transistor) 2 formed by a PMOS (p-channel MOS) transistor. The FET 2 has a source thereof supplied with a power supply voltage of 5 volts, and a drain thereof connected to an internal circuit 3. This circuit configuration enables the FET 2 to function as a driver for supplying electric power to the internal circuit 3, in which the drain voltage VDL of the FET 2 is used as the power supply voltage of the internal circuit 3.
Further, the drain voltage VDL of the FET 2 is divided by a voltage divider formed by a resistance 1 and a resistance 2, and the divided voltage is fed back to a positive input terminal of the operational amplifier 1. On the other hand, the operational amplifier 1 has a negative input terminal thereof supplied with a reference voltage Vref. Therefore, when the voltage applied to the positive input terminal exceeds the reference voltage Vref, the output voltage of the operational amplifier 1 rises to turn the FET 2 off, which decreases the drain voltage VDL of the FET 2. When the voltage at the positive input terminal of the operational amplifier 1 becomes lower than the reference voltage Vref, the output voltage of the operational amplifier 1 decreases to turn the FET 2 on, which increases the drain voltage VDL of the FET 2. Thus, the voltage dropping circuit is constituted as a negative feedback amplifier comprised of the operational amplifier 1 and the FET 2 connected in series, whereby the drain voltage VDL is supplied as a stable voltage to the internal circuit. In the illustrated example, by setting the resistance R1 to a value of 8 K .OMEGA., the resistance R2 to a value of 25 K .OMEGA., and the reference voltage Vref to a value of 2.5 volts, a drain voltage VDL of 3.3 volts can be obtained.
In the conventional voltage dropping circuit, the drivability of the p-channel driver formed by the FET 2 and the dropped voltage (drain voltage VDL) depend on a variation in the load on the internal circuit 3 and an operation margin of the same. Assuming that the allowable lower limit voltage of the operation margin is 3 volts under the worst operating conditions (of operation of transistors, including the environmental temperature), for instance, the dropped voltage VDL has to be maintained at 3 volts even if the load on the internal circuit 3 varies. If a margin of 0.3 volts is allowed for the required power supply voltage, the dropped voltage VDL is set to 3.3 volts. Then, under the best conditions (the best conditions of operation of transistors, including the environmental temperature, and the worst conditions of the external power supply voltage), normal operation of the internal circuit has to be ensured even if the load on the internal circuit 3 varies. In short, the drivability of the FET 2 (p-channel driver) is determined under these conditions.
Now, provided that a change in the gate voltage which occurs when a load current flowing through the internal circuit 3 has changed from a value I.sub.B to a value I.sub.L is represented by .DELTA.Vi, and a change in the drain voltage on the same occasion by .DELTA.Vo, the following equations (1) and (2) hold: ##EQU1##
From the equations (1) and (2), the following equation can be obtained: ##EQU2## where Cc represents a Miller capacitance, Cg a gate capacitance of the FET, W a total width of the FET, and L a length of the same.
Now, let it be assumed that Cc=200 PF, Cox=2.0 F/ .mu.m.sup.2, L=0.6 .mu.m, and K'=10 .mu.A/V.sup.2, and it is required to limit the change .DELTA.Vo to 0.3 volts in cases where the variation in the load on the internal circuit 3 is in a range of 10 mA to 80 mA under the worst conditions and in a range of 10 mA to 100 mA under the best conditions. If these conditions are applied to the equation (3), a conforming FET has to fulfill W&gt;31600 .mu.m under the worst conditions, and W&gt;55400 .mu.m under the best conditions.
It will be noted from the above description that to ensure that the dropped voltage VDL obtained under the worst conditions can be obtained under the best conditions, it is required to increase the area of the FET 2. On the other hand, the peak current flowing through the internal circuit 3 under the best conditions tends to become larger than that under the worst conditions. Therefore, even where there is no problem in increasing the area, if settings are made so as to ensure the supply of the dropped voltage VDL under the worst conditions to the voltage dropping circuit even under the best conditions, a larger consumption current flows.